VideoBrain Family Computer

VideoBrain Picture (From http://armchairarcade.com/neo/node/3415


Index of Site:


Books
Discussion Group
F8 and VideoBrain Programming (and Source Code)
Links
Magazine Articles
Programming Books/Manuals
Search Site Using Google Search
VideoBrain Emulation (Nothing Yet)
VideoBrain Manuals
VideoBrain Software
What's New



Books


History of the Personal Computer

 
Stan Veit's History of the Personal Computer (excerpt)
By Stan Veit
Copyright 1993

This condensed "history" of the VideoBrain is from Chapter 21, Dogs and Dinosaurs, of the book "Stan Veit's History of the Personal Computer," by Stan Veit. The history is told very informally, yet it does give a glimpse of information that I've never read before about the VideoBrain. Stan seems more interested in telling a good story than getting the facts straight, as I've found several errors in the book. Still, Stan is part of the early computer history (he was the first owner of a computer store on the east coast of the United States) and his insight here is first-hand knowledge.

You can read the entire short chapter, or just read the excerpts directly related to the VideoBrain in a text file here.




Magazine Articles


Critique of the F8 Microprocessor

 
Opinion: Critique of the F8 Microprocessor
By Dave Caulkins
Source: Computer, Vol. 10, No. 8 (August 1977): 83-86.

From Introduction:

The Fairchild is a control microprocessor whose architecture is considerably different from most machines in the same price and performance class. Good computer architecture is consistent, symmetrical, and coherent; the programmer is provided with the maximum amount of information possible after each operation and his freedom of action is limited as little as possible. A machine with these qualities behaves in the way one expects it to behave; it is free of special cases and peculiar quirks. The F8 falls considerably short of meeting these goals. It predates most equivalent micros; its designers seem to had little contact with designers doing similar things This background has resulted in a machine combining brilliant design concepts with ugly flaws.

Two of the brilliant concepts deserve special mention

  1. The F8 CPU (3850) has allocated a scarce resource, package pins, in a novel way. Instead of a conventional address bus, there are two 8-bit I/O ports. A bidirectional 8-bit data bus and eight control lines provide all required communication between the 3850 and associated Program and data counters (PC and DC respectively) are resident outside the 3850.
  2. The 3850 has 64 bytes of resident scratchpad memory. The power of these features is indicated by the fact that similar controller-type machines of much more recent., vintage (the Intel 8048 comes to mind) provide very similar capabilities.

The F8 flaws are covered in detail [in the article]. On balance, I think the advantages outweigh the flaws, but they turn the F8 from what might have been a really nice machine into one which is cost effective but exasperating to use.

If you prefer to read the introduction in text format, which includes additional information about the source of the scans, then it can be read here.



VideoBrain: The Consumer Computer

 
VideoBrain: The Consumer Computer
By Mike Peak
Source: Interface Age, Vol. 3, No. 2 (February 1978): 104-105.

From Article:

The industry is now viewing the microprocessor, not only for games, but for viable home computing systems. One company in particular, VideoBrain of Sunnyvale, California, has recently developed one of the more exciting entrants to the new field of consumer computers. This new device is named the VideoBrain.

The VideoBrain is the first true turnkey computer system built with the general consumer in mind. Built around the F8 microprocessor the VideoBrain does not require any computer expertise on the part of the user.

The VideoBrain is designed to be the very first computer system to take full advantage of current technological know-how, and remove the mystery surrounding computers. The VideoBrain provides for man machine interface by utilizing familiar objects found in the home, the color TV and telephone. The basic application design provides something for everyone with the greatest emphasis placed on the homemaker.

If you prefer to read the article in text format, which is missing the pictures and the block diagram, it can be read here.

 


Programming Books/Manuals


F8 Microprocessor System Patent #4086626

 
F8 Microprocessor System Patent
U.S. #4086626
Fairchild Camera and Instrument Corporation
Patent Filed June 7, 1976 and Granted April 25, 1978


Following are the patent's "abstract" and "summary of invention" taken directly from the F8 patent:

Abstract

A microprocessor system having at least two separate scale integration devices. A first of the two large scale integration devices is a central processing unit formed on a single semiconductor die, and the second large scale integration device is a memory circuit formed on a separate single semiconductor die. The term "die" as used herein is conventional and refers to a unitary semiconductor body or chip. The central processing unit requires an external program counter which contains memory addresses of instruction codes to be used by the central processing unit. The memory device is electrically coupled to the central processing unit and includes a memory for storing the instruction codes, and a program counter for addressing the memory. Provision is made to incorporate additional memory circuits to expand the size and capability of the microprocessor system. System interrupt circuitry is also provided for interrupting system operation to change to a new sequence of instruction codes.

Summary of the Invention

In accordance with the present invention, a microprocessor system is provided which has at least two separate large scale integration devices comprising a central processing unit large scale integration device including an arithmetic logic unit and at least one input/output port. The central processing unit requires an external program counter containing memory addresses of instruction codes to be used by the central processing unit. A first memory large scale integration device is provided which is electrically coupled to said central processing unit and includes a memory and the program counter. The program counter cooperates with the first central processing unit large scale integration device to select the instruction codes for operating the microprocessor in a manner determined by the instruction codes.

The microprocessor system of the present invention incorporates a single-chip central processing unit of large scale integration which contains the standard elements of a central processing unit including input-and-output ports, a program logic array, an arithmetic logic unit, and a scratch pad memory; but which does not contain a program counter. At least one separate memory large scale integration device on a single chip is also provided which contains its own dedicated program counter. The dedicated program counter is driven in synchronism with the operation of the central processing unit so that appropriate control signals are transmitted from the central processing unit to control the program counter. If more than one separate memory large scale integration device is incorporated in the microprocessor system, each additional memory device includes its own dedicated program counter which operates in synchronism with the central processing unit. In these multiple-memory systems, the dedicated program counters operate in response to control signals from the central processing unit so that each memory will provide instruction codes at the appropriate time to the central processing unit.

An advantage of the system of the present invention is that a minimum number of separate components are required to construct a microprocessor system. That is, a basic microprocessor system is implemented with only two semiconductor chips.

Another advantage of the present invention is that the circuitry required for input-and-output device coupling is minimized. That is, separate clocking circuits for input-and-output devices has been eliminated.

Still another advantage of the present invention is that the system architecture takes advantage of restrictions imposed on large scale integration of semiconductor devices.

 
 
F8 User's Guide (Document #67095665)

 
F8 User's Guide (Document #67095665)
Fairchild Camera and Instrument Corporation
February 1976

This is the 418-page F8 User's Guide (Fairchild Document #67095665). It contains general background about using the F8 system as well as the detailed information required to build a system that uses the F8 CPU and it's support chips. Simple single-processor setups as well as more complicated systems that use multi-processors are explained. The VideoBrain patents refer to this document, as does the article "Opinion: Critique of the F8 Microprocessor" in the August 1977 issue of "Computer."

The guide has eleven sections with information. Sections 8-10 are listed in the table of contents as "pending." No description of what the missing "pending" sections is supposed to hold is given. The sections, including the empty ones, are listed here:

  1. The F8 Microcomputer System
  2. The 3850 CPU
  3. The 3851 Program Storage Unit (PSU)
  4. The 3852 Dynamic Memory Interface (DMI)
  5. The 3853 Static Memory Interface (SMI)
  6. The 3854 Direct Memory Access Controller (DMA)
  7. The 3861 Peripheral Input/Output (PIO)
  8. Pending [Empty, Not Included in Book]
  9. Pending [Empty, Not Included in Book]
  10. Pending [Empty, Not Included in Book]
  11. 3850 CPU-3851 PSU Systems
  12. F8 Configurations That Include 3852 DMI and 3853 SMI Devices
  13. Using Direct Memory Access
  14. Multiprocessor Configurations and Applications

An appendix and six datasheets are also included:

  1. Appendix A: FAIR-BUG - 3851A PSU (SL 31162) Specification
  2. Datasheet 1: Fairchild 3539 (256 x 8 Static RAM)
  3. Datasheet 2: Fairchild 2102 (1024 x 1 Static RAM)
  4. Datasheet 3: Fairchild 4096 (4096 x 1 Dynamic RAM)
  5. Datasheet 4: Fairchild 3516 (16-Bit MOS ROM)
  6. Datasheet 5: Fairchild 93436/93446 (Isoplaner Schottky TTL Memory, 512 x 4 Bit PROM)
  7. Datasheet 6: Fairchild 93438/93448 (Isoplaner Schottky TTL Memory, 512 x 8 Bit PROM)
 
 
F8 User's Manual

 
F8 User's Manual (Preliminary)
Fairchild Semiconductor
January 1975

This is the 193-page preliminary version of the F8 User's Manual. Here is the introduction to the manual:

The F8 System is designed to provide the engineer the maximum benefits possible in the area of reduced costs and high performance. There are approximately 70 instructions available most of which are single byte in length. More complicated functions and addressing modes are eliminated to compact total circuit size and thereby reduce costs. The instructions, as a consequence, are easy to learn and simple to use facilitating easier program design and shorter development time.

The design of the F8 circuits has been carefully planned to provide the most useful functions possible in the limited chip area of reasonably producible circuits. Partitioning of the internal logic has been arranged to provide the maximum utilitarian use of the available external circuit interconnections. For example, the program counter has been located in the memory circuits eliminating the need for 16 address connections between F8 circuits. Input/Output ports have been added to both the CPU and the F8 ROM circuits and brought out to the now available 16 pins on each circuit to give the designer more utilitarian functions available for implementing his design.

A fully functional F8 microprocessor based system can be fabricated with as few as only (2) F8 circuits and some passive components (resistors and capacitors). Typical applications for the 2 circuit configuration are noncomplicated control or business machine applications: Yet, the F8 has the power and flexibility to be used in more complex systems having up to 65,536 bytes of total addressable memory, direct memory access and multiple level priority interrupts.

Additional circuits are included to add flexibility and minimize the total system package count. The clock generator circuit and power-on detect circuits are included in the CPU circuit to simplify system design. Each memory chip contains a programmable timer to facilitate generating real time events or delays without disabling the processor. (The usual method of creating time delays ties up the processor counting non-functional instructions in a loop until the desired elapsed time has occurred.)

A RAM of sixty-four words of 8 bits each is included in the CPU as a fast operating scratchpad register array. Instructions that use the RAM (ADD, LOAD, OR, AND, Decrement, et al) all execute within 2 microseconds (The Decimal ADD requires 4 usec. and the Decrement REQUIRES 3 usec).

The entire introduction, in text format, in available, here.

 
 
F8 Guide To Programming

 
Guide to Programming the F8 Microprocessor
Fairchild Camera & Instrument Corp.
Document #67095664
Copyright 1976

Here is the introduction to the manual:

This manual explains how to write programs for the Fairchild F8 microprocessor system, and how these F8 programs cause a microprocessor system to function as a discrete logic replacement.

The Fairchild F8 family of logic devices consists of a Central Processing Unit and a number of complementary devices, manufactured using n-channel Isoplanar MOS technology. Components of the F8 family include the following devices:

  1. The 3850 Central Processing Unit (CPU)
  2. The 3851 Program Storage Unit (PSU)
  3. The 3852 Dynamic Memory Interface (DMI)
  4. The 3853 Static Memory Interface (SMI)
  5. The 3854 Direct Memory Access (DMA)

Complete microprocessor based systems may vary in size and complexity from as little as two devices- the 3850 CPU and the 3851 PSU- to large systems incorporating the above five devices, plus any standard static and/or dynamic Random Access Memory (RAM) devices. The following are some general characteristics of this micro-processor device set:

If you want to read the entire introduction, which includes sections called "Assumed Reader Background" and "Supporting Documentation" then it is available, here.

 
 
Videobrain Video Hardware Patent (US 4177462)

 
VideoBrain Video Hardware Description
U.S. #4,177,462
Umtech, Inc.
Patent Filed Dec. 30, 1976 and Granted Dec. 4, 1979

The VideoBrain's U.S. patent #4,177,462, is called "Computer Control of Television Receiver Display." It is a 27-page technical document by David H. Chung. The abstract, like most patents, is very specific:

"A method and apparatus for generating, under the control of a microprocessor, signals for operating a visual display mechanism of the scanning type. The position of the scan is tracked, and when it approaches a desired location on the display area for a particular segment to be displayed, it responds thereto by directing delivery to the scanning system of control signals which define the selected. display segment. A plurality of display segments, each containing information at least partially defining one or more object images which it may be desired to be included in a specified display, are stored in a cartridge memory which can also include specific operating instructions for carrying out a particular game or other function with such display segments. Each of the display composers includes an associative memory arrangement for addressing the cartridge memory and directing feedout therefrom of specified segments at times required during the scan. A FIFO buffer is also included in each of the display composers for delivering information defining an object image at a regular rate correlated to the scanning rate, irrespective of the time in which such information is made ready for the display."

Kurt Woloch, a member of the Channel F and VideoBrain Yahoo discussion group, shared his concise thoughts with the group about the patent. here.

 
 
Videobrain Video Hardware Patent (US 4232374)

 
VideoBrain Video Hardware Description
U.S. #4,232,374
Umtech, Inc.
Patent Filed Aug. 11, 1977 and Granted Nov. 4, 1980

The actual name of this patent is "Segment Ordering for Television Receiver Control Unit" (U.S. Patent #4232374) by Chung, et al. That sure is a mouthful-- and it doesn't exactly make it obvious that this patent has anything to do with the VideoBrain computer. The patent was applied for in 1977 and wasn't granted to Umtech, Inc. until November 4, 1980, well after the VideoBrain had already left the marketplace. The inventers of this "apparatus" are David H. Chung and John V. Cosley. Here is the abstract, absorb from it what you can:

"A method and apparatus are described for generating, under the control of a microprocessor, signals for operating a scanning system of a standard television receiver. A plurality of display segments, each containing information at least partially defining one or more object images that may be desired be included in a specified display on the receiver, are stored in a cartridge memory which can also include specific operating instructions for carrying out a particular video game or other function with such display segments. Indicia uniquely associated with each of the display segments are placed in a predetermined order correlated with the order of appearance in the display of those display segments which are to be included therein. The position of the scan is tracked, and when it approaches a desired location under the display area for a particular segment to be displayed, it responds to the indicia representing such segment by directing delivery to the scanning system of control signals which define the selected display segment. The apparatus includes composers for producing the display for each line, and a FIFO buffer for delivering information defining the line to the scanning system at a regular rate correlated to the scanning rate, irrespective of the time in which such information is made ready for the display."

If you're anything like me, than the abstract for the patent made absolutely no sense to you. Kurt Woloch wrote a handy overview of the entire patent written in understandable language. You can read the overview here. Also, of note, I've noticed that this pdf doesn't display properly with older versions of Acrobat Reader and it requires the newest version to be installed.

 


Discussion Group


The VideoBrain is not the only computer to use the Fairchild F8 CPU. Among other systems, the Channel F from 1976 (notably the first cartridge-based videogame console) also used the F8. There is an active Channel F and VideoBrain discussion group over at Yahoo Groups. Why not come by and say hello?

Click here to join ballyalley
Click to join the Channel F / VideoBrain Discussion Group



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